■ Invalid Data Interrupt: Signals when a bit in Flash that was previously programmed as a 0 is now
requested to be programmed as a 1. (INVDRIS).
■ ERASE Operation Interrupt: Indicates an ERASE operation failed. (ERRIS).
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 633) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 630).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 635).
8.2.3.9 µDMA
The µDMA can be programmed to read from Flash. The Flash DMA Address Size (FLASHDMASZ)
register configures 2-KB regions of Flash that can be accessed by the µDMA. The starting address
for this µDMA-accessible region is defined in the Flash DMA Starting Address (FLASHDMAST)
register. When the DFA bit is set in the FLASHPP register, the µDMA can access the enabled region
configured by the FLASHDMASZ and FLASHDMAST registers. The µDMA checks the Flash
Protection Program Enable n (FMPPEn) registers for masked 2-KB Flash regions before initiating
the transfer. If the access is out of range, then a bus fault is generated.
Note: The µDMA can access Flash in Run Mode only (not available in low power modes).
8.2.3.10 Flash Memory Programming
The Tiva™ C Series devices provide a user-friendly interface for Flash memory programming. All
erase/program operations are handled via three registers: Flash Memory Address (FMA), Flash
Memory Data (FMD), and Flash Memory Control (FMC). Note that if the debug capabilities of the
microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be
performed in order to reactivate the debug module. See “Recovering a "Locked"
Microcontroller” on page 213.
When a Flash memory operation write, page erase, or mass erase is executed in a Flash bank,
access to that particular bank pair is inhibited. As a result, instruction and literal fetches to the bank
pair are held off until the Flash memory operation is complete. If instruction execution is required
during a Flash memory operation, the code that is executing must be placed in SRAM and executed
from there while the flash operation is in progress.
Note: When programming Flash memory, the following characteristics of the memory must be
considered:
■ Only an erase can change bits from 0 to 1.
■ A write can only change bits from 1 to 0. If the write attempts to change a 0 to a 1, the
write fails and no bits are changed.
■ All Flash operations are completed before entering sleep or deep sleep.
To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
June 18, 2014612
Texas Instruments-Production Data
Internal Memory
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