DescriptionResetTypeNameBit/Field
Extended Drive Mode Bit 0
This field controls extended drive modes of bit 0 of the GPIO port.
Note that depending on the encoding used the GPIO drive strength
control registers may change their decoding. Moreover, the write one,
clear other register behavior may be disabled.
DescriptionValue
Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive
Select (GPIODRnR) registers function as normal.
0x0
An additional 6 mA option is provided.
Write one, clear other behavior of GPIODDRnR registers is
disabled.
A 2 mA driver is always enabled; setting the corresponding
GPIODR4R register bit adds 2 mA and setting the corresponding
GPIODR8R register bit adds an additional 4 mA.
0x1
reserved0x2
Additional drive strength options of 6, 10, and 12 mA are
provided.
The write one, clear other behavior of GPIODDRnR registers
is disabled.
A 2 mA driver is always enabled; setting the corresponding
GPIODR4R register bit adds 2 mA and setting the corresponding
GPIODR8R of GPIODR12R register bit adds an additional 4
mA.
0x3
0RWEDM01:0
June 18, 2014802
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
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