DescriptionResetTypeNameBit/Field
Clock Gated
DescriptionValue
The EPI clock is free running.0
The EPI clock is held low.1
Note: A software application should only set the CLKGATE bit when
there are no pending transfers or no EPI register access has
been issued.
0RWCLKGATE31
Clock Gated when Idle
DescriptionValue
The EPI clock is free running.0
The EPI clock is output only when there is data to write or read
(current transaction); otherwise the EPI clock is held low.
1
Note that EPI0S32 is an iRDY signal if RDYEN is set. CLKGATEI is
ignored if CLKPIN is 0 or if the COUNT0 field in the EPIBAUD register
is cleared.
0RWCLKGATEI30
Invert Output Clock Enable
DescriptionValue
No effect.0
Invert EPI clock to ensure the rising edge is centered for
outbound signal's setup and hold. Inbound signal is captured
on rising edge EPI clock.
1
0RWCLKINV29
Input Ready Enable
DescriptionValue
No effect.0
An external ready can be used to control the continuation of the
current access. If this bit is set and the iRDY signal (EPIS032)
is low, the current access is stalled.
1
0RWRDYEN28
Input Ready Invert
DescriptionValue
No effect.0
Invert the polarity of incoming external ready (iRDY signal). If
this bit is set and the iRDY signal (EPIS032) is high the current
access is stalled.
1
0RWIRDYINV27
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved26:24
June 18, 2014866
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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