DescriptionResetTypeNameBit/Field
External FIFO FULL Enable
DescriptionValue
No effect.0
An external FIFO full signal can be used to control write cycles.
If this bit is set and the FFULL full signal is high, XFIFO writes
are stalled.
1
0RWXFFEN23
External FIFO EMPTY Enable
DescriptionValue
No effect.0
An external FIFO empty signal can be used to control read
cycles. If this bit is set and the FEMPTY signal is high, XFIFO
reads are stalled.
1
0RWXFEEN22
WRITE Strobe Polarity
DescriptionValue
The WRITE strobe for CS0n is WRn (active Low).0
The WRITE strobe for CS0n is WR (active High).1
0RWWRHIGH21
READ Strobe Polarity
DescriptionValue
The READ strobe for CS0n is RDn (active Low).0
The READ strobe for CS0n is RD (active High).1
0RWRDHIGH20
ALE Strobe Polarity
DescriptionValue
The address latch strobe for CS0n accesses is ALEn (active
Low).
0
The address latch strobe for CS0n accesses is ALE (active
High).
1
1RWALEHIGH19
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved18:16
Maximum Wait
This field defines the maximum number of external clocks to wait while
an external FIFO ready signal is holding off a transaction (FFULL and
FEMPTY).
When the MAXWAIT value is reached the ERRRIS interrupt status bit
is set in the EPIRIS register. When this field is clear, the transaction can
be held off forever without a system interrupt.
Note: When the MODE field is configured to be 0x2 and the BLKEN
bit is set in the EPICFG register, enabling HB8 mode, this
field defaults to 0xFF.
0xFFRWMAXWAIT15:8
867June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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