DescriptionResetTypeNameBit/Field
External FIFO FULL Enable
DescriptionValue
No effect.0
An external FIFO full signal can be used to control write cycles.
If this bit is set and the FFULL signal is high, XFIFO writes are
stalled.
1
0RWXFFEN23
External FIFO EMPTY Enable
DescriptionValue
No effect.0
An external FIFO empty signal can be used to control read
cycles. If this bit is set and the FEMPTY signal is high, XFIFO
reads are stalled.
1
0RWXFEEN22
WRITE Strobe Polarity
DescriptionValue
The WRITE strobe for CS0n is WRn (active Low).0
The WRITE strobe for CS0n is WR (active High).1
0RWWRHIGH21
READ Strobe Polarity
DescriptionValue
The READ strobe for CS0n is RDn (active Low).0
The READ strobe for CS0n is RD (active High).1
0RWRDHIGH20
ALE Strobe Polarity
DescriptionValue
The address latch strobe for CS0n is ALEn (active Low).0
The address latch strobe for CS0n is ALE (active High).1
1RWALEHIGH19
PSRAM Configuration Register Write
Used for PSRAM configuration registers.
With WRCRE set, the next transaction by the EPI will be a write of the CR
bit field in the EPIHBPSRAM register to the configuration register (CR)
of the PSRAM. The WRCRE bit will self clear once the write-enabled CRE
access is complete.
DescriptionValue
No Action.0
Start CRE write transaction for CS0n.1
0RWWRCRE18
June 18, 2014872
Texas Instruments-Production Data
External Peripheral Interface (EPI)