DescriptionResetTypeNameBit/Field
PSRAM Configuration Register Read
Enables read of PSRAM configuration registers.
With the RDCRE set, the next access is a read of the PSRAM's
Configuration Register (CR). This bit self clears once the read-enabled
CRE access is complete. The address for the CRE access is located
at EPIHBPSRAM[19:18]. The read data is returned on
EPIHBPSRAM[15:0].
DescriptionValue
No Action.0
Start CRE read transaction for CS0n.1
0RWRDCRE17
Burst Mode
Burst mode must be used with an ALE-enabled interface. Burst mode
must be used with ADMUX, which is configured by the MODE field in the
EPIHB16CFG register.
Note: Burst mode is optimized for word-length accesses.
DescriptionValue
Burst mode is disabled.0
Burst mode is enabled for CS0n or single chip access.1
0RWBURST16
Maximum Wait
This field defines the maximum number of external clocks to wait while
an external FIFO ready signal is holding off a transaction (FFULL and
FEMPTY).
When this field is clear, the transaction can be held off forever without
a system interrupt.
Note: When the MODE field is configured to be 0x3 and the BLKEN
bit is set in the EPICFG register, enabling HB16 mode, this
field defaults to 0xFF.
0xFFRWMAXWAIT15:8
Write Wait States
This field adds wait states to the data phase of CS0n (the address phase
is not affected). The effect is to delay the rising edge of WRn (or the
falling edge of WR). Each wait state adds 2 EPI clock cycles to the
access time. The WRWSM bit EPIHB16TIME register can decrease the
number of wait states by 1 EPI clock cycle for greater granularity. This
field is not applicable in BURST mode.
DescriptionValue
Active WRn is 2 EPI clocks.0x0
Active WRn is 4 EPI clocks.0x1
Active WRn is 6 EPI clocks.0x2
Active WRn is 8 EPI clocks.0x3
This field is used in conjunction with the EPIBAUD register.
0x0RWWRWS7:6
873June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
To Next Page
Loading...
Need help?
General
