DescriptionResetTypeNameBit/Field
Read Wait States
This field adds wait states to the data phase of CS0n (the address phase
is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of
RD). Each wait state adds 2 EPI clock cycles to the access time. The
RDWSM bit in the EPIHB16TIME register can decrease the number of
wait states by 1 EPI clock cycle for greater granularity. This field is not
applicable in BURST mode.
DescriptionValue
Active RDn is 2 EPI clocks.0x0
Active RDn is 4 EPI clocks.0x1
Active RDn is 6 EPI clocks.0x2
Active RDn is 8 EPI clocks.0x3
This field is used in conjunction with the EPIBAUD register
0x0RWRDWS5:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
Byte Select Configuration
This bit enables byte select operation.
DescriptionValue
No Byte Selects
Data is read and written as 16 bits.
0
Enable Byte Selects
Two EPI signals function as byte select signals to allow 8-bit
transfers. See Table 11-9 on page 833 for details on which EPI
signals are used.
1
Note: If BSEL = 0, byte accesses cannot be executed.
0RWBSEL2
June 18, 2014874
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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