DescriptionResetTypeNameBit/Field
Chip Select Configuration
This field controls the chip select options, including an ALE format, a
single chip select, two chip selects, and an ALE combined with two chip
selects. These bits are also used in combination with the CSCFGEXT bit
for further configurations, including quad- chip select.
DescriptionValue
ALE Configuration
EPI0S30 is used as an address latch (ALE). The ALE signal is
generally used when the address and data are muxed (HB8MODE
field in the EPIHB8CFG register is 0x0). The ALE signal is used
by an external latch to hold the address through the bus cycle.
0x0
CSn Configuration
EPI0S30 is used as a Chip Select (CSn). When using this mode,
the address and data are generally not muxed (HB8MODE field
in the EPIHB8CFG register is 0x1). However, if address and
data muxing is needed, the WR signal (EPI0S29) and the RD
signal (EPI0S28) can be used to latch the address when CSn
is low.
0x1
Dual CSn Configuration
EPI0S30 is used as CS0n and EPI0S27 is used as CS1n.
Whether CS0n or CS1n is asserted is determined by two
methods. If only external RAM or external PER is enabled in
the address map, the most significant address bit for a
respective external address map controls CS0n or CS1n. If both
external RAM and external PER is enabled, CS0n is mapped
to PER and CS1n is mapped to RAM. This configuration can
be used for a RAM bank split between 2 devices as well as
when using both an external RAM and an external peripheral.
0x2
ALE with Dual CSn Configuration
EPI0S30 is used as address latch (ALE), EPI0S27 is used as
CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n
is asserted is determined by the most significant address bit for
a respective external address map.
0x3
0x0RWCSCFG25:24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved23:22
CS1n WRITE Strobe Polarity
This field is used if the CSBAUD bit in the EPIHB8CFG2 register is
enabled.
DescriptionValue
The WRITE strobe for CS1n accesses is WRn (active Low).0
The WRITE strobe for CS1n accesses is WR (active High).1
0RWWRHIGH21
June 18, 2014882
Texas Instruments-Production Data
External Peripheral Interface (EPI)
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