DescriptionResetTypeNameBit/Field
CS1n READ Strobe Polarity
This field is used if the CSBAUD bit in the EPIHB8CFG2 register is
enabled.
DescriptionValue
The READ strobe for CS1n accesses is RDn (active Low).0
The READ strobe for CS1n accesses is RD (active High).1
0RWRDHIGH20
CS1n ALE Strobe Polarity
This field is used if the CSBAUD bit in the EPIHB8CFG2 register is
enabled.
DescriptionValue
The address latch strobe for CS1n accesses is ALEn (active
Low).
0
The address latch strobe for CS1n accesses is ALE (active
High).
1
1RWALEHIGH19
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved18:8
CS1n Write Wait States
This field adds wait states to the data phase of CS1n accesses (the
address phase is not affected).
The effect is to delay the rising edge of WRn (or the falling edge of WR).
Each wait state encoding adds 2 EPI clock cycles to the access time.
The WRWSM bit in the EPIHB8TIME2 register can decrease the number
of wait states by 1 EPI clock cycle for greater granularity.
This field is used if the CSBAUD bit is enabled in the EPIHB8CFG2
register. This field is used in conjunction with the EPIBAUD register and
is not applicable in BURST mode.
DescriptionValue
Active WRn is 2 EPI clocks.0x0
Active WRn is 4 EPI clocks0x1
Active WRn is 6 EPI clocks0x2
Active WRn is 8 EPI clocks0x3
0x0RWWRWS7:6
883June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
To Next Page
Loading...
Need help?
General
