Register 54: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ..................................... 1153
Register 55: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C .................................... 1153
Register 56: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ..................................... 1156
Register 57: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ..................................... 1156
Register 58: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ..................................... 1156
Register 59: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C .................................... 1156
Register 60: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ..................................... 1156
Register 61: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ..................................... 1156
Register 62: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ..................................... 1156
Register 63: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C .................................... 1156
Register 64: ADC Peripheral Properties (ADCPP), offset 0xFC0 ........................................................ 1157
Register 65: ADC Peripheral Configuration (ADCPC), offset 0xFC4 ................................................... 1159
Register 66: ADC Clock Configuration (ADCCC), offset 0xFC8 .......................................................... 1160
Universal Asynchronous Receivers/Transmitters (UARTs) ................................................... 1161
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................. 1175
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ......................... 1177
Register 3: UART Flag (UARTFR), offset 0x018 .............................................................................. 1180
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................ 1183
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 .......................................... 1184
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ..................................... 1185
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................. 1186
Register 8: UART Control (UARTCTL), offset 0x030 ........................................................................ 1188
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 .......................................... 1192
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................ 1194
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C .................................................... 1198
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ............................................... 1202
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 .............................................................. 1206
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 ........................................................ 1208
Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................. 1209
Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................. 1210
Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0 .................................................... 1211
Register 18: UART Clock Configuration (UARTCC), offset 0xFC8 ...................................................... 1213
Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ................................... 1214
Register 20: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ................................... 1215
Register 21: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ................................... 1216
Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ................................... 1217
Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 .................................... 1218
Register 24: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 .................................... 1219
Register 25: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 .................................... 1220
Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ................................... 1221
Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ...................................... 1222
Register 28: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ...................................... 1223
Register 29: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ...................................... 1224
Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ...................................... 1225
Quad Synchronous Serial Interface (QSSI) ............................................................................. 1226
Register 1: QSSI Control 0 (SSICR0), offset 0x000 ......................................................................... 1245
Register 2: QSSI Control 1 (SSICR1), offset 0x004 ......................................................................... 1247
Register 3: QSSI Data (SSIDR), offset 0x008 ................................................................................. 1249
37June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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