Texas Instruments TM4C1294NCPDT User Manual

Register 4: QSSI Status (SSISR), offset 0x00C ............................................................................... 1250
Register 5: QSSI Clock Prescale (SSICPSR), offset 0x010 .............................................................. 1252
Register 6: QSSI Interrupt Mask (SSIIM), offset 0x014 .................................................................... 1253
Register 7: QSSI Raw Interrupt Status (SSIRIS), offset 0x018 ......................................................... 1255
Register 8: QSSI Masked Interrupt Status (SSIMIS), offset 0x01C ................................................... 1257
Register 9: QSSI Interrupt Clear (SSIICR), offset 0x020 .................................................................. 1259
Register 10: QSSI DMA Control (SSIDMACTL), offset 0x024 ............................................................. 1260
Register 11: QSSI Peripheral Properties (SSIPP), offset 0xFC0 ......................................................... 1261
Register 12: QSSI Clock Configuration (SSICC), offset 0xFC8 ........................................................... 1262
Register 13: QSSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ........................................ 1263
Register 14: QSSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ........................................ 1264
Register 15: QSSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ........................................ 1265
Register 16: QSSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ........................................ 1266
Register 17: QSSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ........................................ 1267
Register 18: QSSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ........................................ 1268
Register 19: QSSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ........................................ 1269
Register 20: QSSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ........................................ 1270
Register 21: QSSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ........................................... 1271
Register 22: QSSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ........................................... 1272
Register 23: QSSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ........................................... 1273
Register 24: QSSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .......................................... 1274
Inter-Integrated Circuit (I
2
C) Interface ...................................................................................... 1275
Register 1: I
2
C Master Slave Address (I2CMSA), offset 0x000 ......................................................... 1302
Register 2: I
2
C Master Control/Status (I2CMCS), offset 0x004 ......................................................... 1303
Register 3: I
2
C Master Data (I2CMDR), offset 0x008 ....................................................................... 1312
Register 4: I
2
C Master Timer Period (I2CMTPR), offset 0x00C ......................................................... 1313
Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010 ....................................................... 1315
Register 6: I
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ............................................... 1318
Register 7: I
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 .......................................... 1321
Register 8: I
2
C Master Interrupt Clear (I2CMICR), offset 0x01C ....................................................... 1324
Register 9: I
2
C Master Configuration (I2CMCR), offset 0x020 .......................................................... 1326
Register 10: I
2
C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 ............................. 1327
Register 11: I
2
C Master Bus Monitor (I2CMBMON), offset 0x02C ....................................................... 1328
Register 12: I
2
C Master Burst Length (I2CMBLEN), offset 0x030 ....................................................... 1329
Register 13: I
2
C Master Burst Count (I2CMBCNT), offset 0x034 ........................................................ 1330
Register 14: I
2
C Slave Own Address (I2CSOAR), offset 0x800 .......................................................... 1331
Register 15: I
2
C Slave Control/Status (I2CSCSR), offset 0x804 ......................................................... 1332
Register 16: I
2
C Slave Data (I2CSDR), offset 0x808 ......................................................................... 1335
Register 17: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x80C ......................................................... 1336
Register 18: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................. 1338
Register 19: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 ............................................ 1341
Register 20: I
2
C Slave Interrupt Clear (I2CSICR), offset 0x818 .......................................................... 1344
Register 21: I
2
C Slave Own Address 2 (I2CSOAR2), offset 0x81C ..................................................... 1346
Register 22: I
2
C Slave ACK Control (I2CSACKCTL), offset 0x820 ...................................................... 1347
Register 23: I
2
C FIFO Data (I2CFIFODATA), offset 0xF00 ................................................................. 1348
Register 24: I
2
C FIFO Control (I2CFIFOCTL), offset 0xF04 ............................................................... 1350
Register 25: I
2
C FIFO Status (I2CFIFOSTATUS), offset 0xF08 .......................................................... 1352
June 18, 201438
Texas Instruments-Production Data
Table of Contents

Texas Instruments TM4C1294NCPDT Specifications

General

Brand	Texas Instruments
Model	TM4C1294NCPDT
Category	Microcontrollers
Language	English