Register 26: I
2
C Peripheral Properties (I2CPP), offset 0xFC0 ............................................................ 1354
Register 27: I
2
C Peripheral Configuration (I2CPC), offset 0xFC4 ....................................................... 1355
Controller Area Network (CAN) Module ................................................................................... 1356
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................ 1378
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................. 1380
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................. 1383
Register 4: CAN Bit Timing (CANBIT), offset 0x00C ........................................................................ 1384
Register 5: CAN Interrupt (CANINT), offset 0x010 ........................................................................... 1385
Register 6: CAN Test (CANTST), offset 0x014 ................................................................................ 1386
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ..................................... 1388
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 .............................................. 1389
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 .............................................. 1389
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 ................................................ 1390
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 ................................................ 1390
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 .............................................................. 1393
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 .............................................................. 1393
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C .............................................................. 1394
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C .............................................................. 1394
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ....................................................... 1396
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ....................................................... 1396
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ....................................................... 1397
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ....................................................... 1397
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 ................................................ 1399
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 ................................................ 1399
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ............................................................... 1402
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................ 1402
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................ 1402
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................ 1402
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ............................................................... 1402
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ............................................................... 1402
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ............................................................... 1402
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ............................................................... 1402
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 .............................................. 1403
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 .............................................. 1403
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ............................................................... 1404
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ............................................................... 1404
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ................................... 1405
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ................................... 1405
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ..................................................... 1406
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ..................................................... 1406
Ethernet Controller .................................................................................................................... 1407
Register 1: Ethernet MAC Configuration (EMACCFG), offset 0x000 ................................................. 1471
Register 2: Ethernet MAC Frame Filter (EMACFRAMEFLTR), offset 0x004 ...................................... 1478
Register 3: Ethernet MAC Hash Table High (EMACHASHTBLH), offset 0x008 .................................. 1482
Register 4: Ethernet MAC Hash Table Low (EMACHASHTBLL), offset 0x00C ................................... 1483
Register 5: Ethernet MAC MII Address (EMACMIIADDR), offset 0x010 ............................................ 1484
Register 6: Ethernet MAC MII Data Register (EMACMIIDATA), offset 0x014 ..................................... 1486
Register 7: Ethernet MAC Flow Control (EMACFLOWCTL), offset 0x018 ......................................... 1487
39June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C1294NCPDT Microcontroller
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