IO Wrap Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.16.440 Register 84Dh (offset = 84Dh) [reset = 2h]
Figure 2-2703. Register 84Dh
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_RXCD_DSA
_GAIN_5
OVR_INTPI_R
XCD_DSA_GAI
N_5
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2719. Register 84D Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
RXCD_DSA_GAIN
_5
R/W 1h
control to select whether the input function
intpi_rxcd_dsa_gain_5 needs to be overriden ot not. 1
indicates override.
0-0
OVR_INTPI_RXCD
_DSA_GAIN_5
R/W 0h override value for ovr_sel_intpi_rxcd_dsa_gain_5 is made high
2.16.441 Register 850h (offset = 850h) [reset = 0h]
Figure 2-2704. Register 850h
7 6 5 4 3 2 1 0
SEL_INTPI_RXCD_DSA_GAINS
EL
POL_INTPI_RX
CD_DSA_GAIN
SEL
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2720. Register 850 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_RXCD
_DSA_GAINSEL
R/W 0h
select control for intpi_rxcd_dsa_gainsel. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_RXCD
_DSA_GAINSEL
R/W 0h
polarity control for intpi_rxcd_dsa_gainsel. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
2.16.442 Register 851h (offset = 851h) [reset = 2h]
Figure 2-2705. Register 851h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_RXCD_DSA
_GAINSEL
OVR_INTPI_R
XCD_DSA_GAI
NSEL
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2721. Register 851 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
RXCD_DSA_GAIN
SEL
R/W 1h
control to select whether the input function
intpi_rxcd_dsa_gainsel needs to be overriden ot not. 1
indicates override.
0-0
OVR_INTPI_RXCD
_DSA_GAINSEL
R/W 0h
override value for ovr_sel_intpi_rxcd_dsa_gainsel is made
high
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