Texas Instruments AFE79 Series - 2.5.31 Register 45 h (offset = 45 h) [reset = 2 h]; 2.5.32 Register 46 h (offset = 46 h) [reset = 1 h]; 2.5.33 Register 47 h (offset = 47 h) [reset = 0 h]

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Serial Interface Register Maps
Table 2-531. Register 44 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
FB_ROOT_CLK_DI
V_M
R/W 2h
M value of root divider.
Output of this divider goes to ddc and jesd clock dividers
2.5.31 Register 45h (offset = 45h) [reset = 2h]
Figure 2-527. Register 45h
7 6 5 4 3 2 1 0
0 0 0 FB_ROOT_CLK_DIV_N_M1
R/W-0h R/W-0h R/W-0h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-532. Register 45 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
FB_ROOT_CLK_DI
V_N_M1
R/W 2h
N value of root divider.
Output of this divider goes to ddc and jesd clock dividers
2.5.32 Register 46h (offset = 46h) [reset = 1h]
Figure 2-528. Register 46h
7 6 5 4 3 2 1 0
0 0 0 DDC_RD_CLK_RX1_DIV_M
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-533. Register 46 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
DDC_RD_CLK_RX
1_DIV_M
R/W 1h
M value of ddc divider.
Output of this divider, clock frequency should match the
RXA/RXC interface rate
2.5.33 Register 47h (offset = 47h) [reset = 0h]
Figure 2-529. Register 47h
7 6 5 4 3 2 1 0
0 0 0 DDC_RD_CLK_RX1_DIV_N_M1
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-534. Register 47 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
DDC_RD_CLK_RX
1_DIV_N_M1
R/W 0h
N-1 value of ddc divider.
Output of this divider, clock frequency should match the
RXA/RXC interface rate