Texas Instruments AFE79 Series - 2.4.102 Register 85 h (offset = 85 h) [reset = 1 h]; 2.4.103 Register 86 h (offset = 86 h) [reset = 1 h]; 2.4.104 Register 87 h (offset = 87 h) [reset = 1 h]; 2.4.105 Register 88 h (offset = 88 h) [reset = 0 h]

DAC JESD Register Map www.ti.com
300
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.4.102 Register 85h (offset = 85h) [reset = 1h]
Figure 2-331. Register 85h
7 6 5 4 3 2 1 0
LANE1_SYNC_ERR_CNT
R-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-335. Register 85 Field Descriptions
Bit Field Type Reset Description
7-0
LANE1_SYNC_ER
R_CNT
R 1h lane1/5 sync error count value read
2.4.103 Register 86h (offset = 86h) [reset = 1h]
Figure 2-332. Register 86h
7 6 5 4 3 2 1 0
LANE2_SYNC_ERR_CNT
R-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-336. Register 86 Field Descriptions
Bit Field Type Reset Description
7-0
LANE2_SYNC_ER
R_CNT
R 1h lane2/6 sync error count value read
2.4.104 Register 87h (offset = 87h) [reset = 1h]
Figure 2-333. Register 87h
7 6 5 4 3 2 1 0
LANE3_SYNC_ERR_CNT
R-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-337. Register 87 Field Descriptions
Bit Field Type Reset Description
7-0
LANE3_SYNC_ER
R_CNT
R 1h lane3/7 sync error count value read
2.4.105 Register 88h (offset = 88h) [reset = 0h]
Figure 2-334. Register 88h
7 6 5 4 3 2 1 0
LANE0_F_COUNTER_ANY_LANE_READY[7:0]
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset