Texas Instruments AFE79 Series - 2.3.114 Register C4 h (offset = C4 h) [reset = 0 h]

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Table 2-157. Register C1 Field Descriptions (continued)
Bit Field Type Reset Description
5-0
APB_CLK_DIV_FA
CTOR
R/W 1h
One hot equivalent divider factor. Final divide value depends
on apb_clk_div_factor_odd register
If apb_clk_divide_factor = 2, and apb_clk_div_factor_odd=1,
the the divide ratio is 5
If apb_clk_divide_factor = 4, and apb_clk_div_factor_odd=1,
the the divide ratio is 7
If apb_clk_divide_factor = 8, and apb_clk_div_factor_odd=1,
the the divide ratio is 9
If apb_clk_divide_factor = 16, and apb_clk_div_factor_odd=1,
the the divide ratio is 11
If apb_clk_divide_factor = 32, and apb_clk_div_factor_odd=1,
the the divide ratio is 13
If apb_clk_divide_factor = 0, and apb_clk_div_factor_odd=1,
the the divide ratio is 15
When dithering is enabled (setting cfg_dithered_mode_en=1),
the divide factor will dynamically change between N and N-1
(one lower than the above mentioned divide factors).
If apb_clk_div_factor = 1, and apb_clk_div_factor_odd=1/0,
the the divide ratio is (3,4)
If apb_clk_div_factor = 2, and apb_clk_div_factor_odd=1, the
the divide ratio is (4,5)
If apb_clk_div_factor = 2, and apb_clk_div_factor_odd=0, the
the divide ratio is (5,6)
If apb_clk_div_factor = 4, and apb_clk_div_factor_odd=1, the
the divide ratio is (6,7)
If apb_clk_div_factor = 4, and apb_clk_div_factor_odd=0, the
the divide ratio is (7,8)
If apb_clk_div_factor = 8, and apb_clk_div_factor_odd=1, the
the divide ratio is (8,9)
If apb_clk_div_factor = 8, and apb_clk_div_factor_odd=0, the
the divide ratio is (9,10)
If apb_clk_div_factor = 16, and apb_clk_div_factor_odd=1, the
the divide ratio is (10,11)
If apb_clk_div_factor = 16, and apb_clk_div_factor_odd=0, the
the divide ratio is (11,12)
If apb_clk_div_factor = 32, and apb_clk_div_factor_odd=1, the
the divide ratio is (12,13)
If apb_clk_div_factor = 32, and apb_clk_div_factor_odd=0, the
the divide ratio is (13,14)
If apb_clk_div_factor = 0, and apb_clk_div_factor_odd=1, the
the divide ratio is (14,15)
If apb_clk_div_factor = 0, and apb_clk_div_factor_odd=0, the
the divide ratio is (15,16)
If apb_clk_divide_factor = 0, and apb_clk_div_factor_odd=1,
the the divide ratio is 15
2.3.114 Register C4h (offset = C4h) [reset = 0h]
Figure 2-155. Register C4h
7 6 5 4 3 2 1 0
APB_CLK_LFS
R_LOAD
APB_CLK_LFS
R_CODE_OVR
_VAL
APB_CLK_FR
OM_MCU_CLK
_EN
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-158. Register C4 Field Descriptions
Bit Field Type Reset Description
2-2
APB_CLK_LFSR_L
OAD
R/W 0h
Loads the LFSR seed value when this is set to 1. Need to be
used along with 'apb_clk_lfsr_seed_val' register
0 : Use default LFSR seed value
1 : Load LFSR seed value from register