Texas Instruments AFE79 Series - 2.6.100 Register 41 FDh (offset = 41 FDh) [reset = 22 h]; 2.6.101 Register 41 FEh (offset = 41 FEh) [reset = B6 h]; 2.6.102 Register 41 FFh (offset = 41 FFh) [reset = 80 h]

SERDES Register Map www.ti.com
498
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.6.100 Register 41FDh (offset = 41FDh) [reset = 22h]
Figure 2-814. Register 41FDh
7 6 5 4 3 2 1 0
VCASGA5X VGAVDSAT[2:1]
R/W-1h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-820. Register 41FD Field Descriptions
Bit Field Type Reset Description
7-5 VCASGA5X R/W 1h
1-0 VGAVDSAT[2:1] R/W 2h
2.6.101 Register 41FEh (offset = 41FEh) [reset = B6h]
Figure 2-815. Register 41FEh
7 6 5 4 3 2 1 0
RX_AC_COUP
LE_EN
VGAVDCOM1 VGAVDCOM2
R/W-1h R/W-3h R/W-3h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-821. Register 41FE Field Descriptions
Bit Field Type Reset Description
7-7
RX_AC_COUPLE_
EN
R/W 1h
Enables RX AC coupling.
0h: DC coupling
1h: AC coupling
6-4 VGAVDCOM1 R/W 3h
3-1 VGAVDCOM2 R/W 3h
2.6.102 Register 41FFh (offset = 41FFh) [reset = 80h]
Figure 2-816. Register 41FFh
7 6 5 4 3 2 1 0
PU_RX_AGC_
LANE
RX_CTLE_BIA
S4
RX_INPUT_EN
R/W-1h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-822. Register 41FF Field Descriptions
Bit Field Type Reset Description
7-7
PU_RX_AGC_LAN
E
R/W 1h
Power up RX AGC by lane.
0h: Power down
1h: Power up
4-4 RX_CTLE_BIAS4 R/W 0h RX CTLE bias setting 4.
3-3 RX_INPUT_EN R/W 0h
Enables RX input.
0h: RX input disabled (Default)
1h: RX input enabled (Required)