Texas Instruments AFE79 Series - 2.5.27 Register 41 h (offset = 41 h) [reset = 2 h]; 2.5.28 Register 42 h (offset = 42 h) [reset = 2 h]; 2.5.29 Register 43 h (offset = 43 h) [reset = 2 h]; 2.5.30 Register 44 h (offset = 44 h) [reset = 2 h]

ADC JESD Register Map www.ti.com
394
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.5.27 Register 41h (offset = 41h) [reset = 2h]
Figure 2-523. Register 41h
7 6 5 4 3 2 1 0
0 0 0 RX1_ROOT_CLK_DIV_N_M1
R/W-0h R/W-0h R/W-0h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-528. Register 41 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
RX1_ROOT_CLK_
DIV_N_M1
R/W 2h
N value of root divider.
Output of this divider goes to ddc and jesd clock dividers
2.5.28 Register 42h (offset = 42h) [reset = 2h]
Figure 2-524. Register 42h
7 6 5 4 3 2 1 0
0 0 0 RX2_ROOT_CLK_DIV_M
R/W-0h R/W-0h R/W-0h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-529. Register 42 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
RX2_ROOT_CLK_
DIV_M
R/W 2h
M value of root divider.
Output of this divider goes to ddc and jesd clock dividers
2.5.29 Register 43h (offset = 43h) [reset = 2h]
Figure 2-525. Register 43h
7 6 5 4 3 2 1 0
0 0 0 RX2_ROOT_CLK_DIV_N_M1
R/W-0h R/W-0h R/W-0h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-530. Register 43 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
RX2_ROOT_CLK_
DIV_N_M1
R/W 2h
N value of root divider.
Output of this divider goes to ddc and jesd clock dividers
2.5.30 Register 44h (offset = 44h) [reset = 2h]
Figure 2-526. Register 44h
7 6 5 4 3 2 1 0
0 0 0 FB_ROOT_CLK_DIV_M
R/W-0h R/W-0h R/W-0h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset