Texas Instruments AFE79 Series - 2.14.4 Register 48 h (offset = 48 h) [reset = 8 h]; 2.14.5 Register 49 h (offset = 49 h) [reset = 4 h]; 2.14.6 Register 4 Ch (offset = 4 Ch) [reset = 0 h]

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Serial Interface Register Maps
Table 2-1900. Register 44 Field Descriptions
Bit Field Type Reset Description
0-0
FB_DDC_REAL_M
ODE_CONFIG
R/W 0h
FB DDC real output mode enable
0: Complex (I/Q) output mode (default)
1: Real (I-only) output mode
2.14.4 Register 48h (offset = 48h) [reset = 8h]
Figure 2-1887. Register 48h
7 6 5 4 3 2 1 0
FB_DDC_FIFO_CONFIG0
R/W-8h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1901. Register 48 Field Descriptions
Bit Field Type Reset Description
3-0
FB_DDC_FIFO_C
ONFIG0
R/W 8h
FB DDC FIFO Configuration0. Value dependent on decimation
factor. Optimal value automatically determined if System
Configuration Macros are used.
2.14.5 Register 49h (offset = 49h) [reset = 4h]
Figure 2-1888. Register 49h
7 6 5 4 3 2 1 0
FB_DDC_FIFO_CONFIG1
R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1902. Register 49 Field Descriptions
Bit Field Type Reset Description
4-0
FB_DDC_FIFO_C
ONFIG1
R/W 4h
FB DDC FIFO Configuration1. Value dependent on decimation
factor. Optimal value automatically determined if System
Configuration Macros are used.
2.14.6 Register 4Ch (offset = 4Ch) [reset = 0h]
Figure 2-1889. Register 4Ch
7 6 5 4 3 2 1 0
FB_DDC_MISC_DLY_CONFIG
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1903. Register 4C Field Descriptions
Bit Field Type Reset Description
1-0
FB_DDC_MISC_D
LY_CONFIG
R/W 0h
Latency-matching delay controls in different FB DDC sections.
Optimal value automatically determined if System
Configuration Macros are used.