Texas Instruments AFE79 Series - 2.14.124 Register 49 Dh (offset = 49 Dh) [reset = 0 h]; 2.14.125 Register 49 Eh (offset = 49 Eh) [reset = 0 h]; 2.14.126 Register 49 Fh (offset = 49 Fh) [reset = 0 h]; 2.14.127 Register 4 A0 h (offset = 4 A0 h) [reset = 32 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.14.124 Register 49Dh (offset = 49Dh) [reset = 0h]
Figure 2-2007. Register 49Dh
7 6 5 4 3 2 1 0
FB_AGC_DEF_
LNA_BYP_VAL
_B0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2021. Register 49D Field Descriptions
Bit Field Type Reset Description
0-0
FB_AGC_DEF_LN
A_BYP_VAL_B0
R/W 0h Default LNA bypass value for Band 0
2.14.125 Register 49Eh (offset = 49Eh) [reset = 0h]
Figure 2-2008. Register 49Eh
7 6 5 4 3 2 1 0
FB_AGC_DEF_
LNA_BYP_VAL
_B1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2022. Register 49E Field Descriptions
Bit Field Type Reset Description
0-0
FB_AGC_DEF_LN
A_BYP_VAL_B1
R/W 0h
Default LNA bypass value for Band1. Applicable only if
rx_agc_dualband_en is made high
2.14.126 Register 49Fh (offset = 49Fh) [reset = 0h]
Figure 2-2009. Register 49Fh
7 6 5 4 3 2 1 0
FB_AGC_DEF_DVGA_ATTN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2023. Register 49F Field Descriptions
Bit Field Type Reset Description
5-0
FB_AGC_DEF_DV
GA_ATTN
R/W 0h
Default Dvga Attn. value when "rx_agc_internal_en" is 0 and
hence it will be starting value when the AGC is enabled
2.14.127 Register 4A0h (offset = 4A0h) [reset = 32h]
Figure 2-2010. Register 4A0h
7 6 5 4 3 2 1 0
FB_AGC_MAX_ATTN
R/W-32h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset