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JESD_SUBCHIP Register Map
163
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-47. Register 24 Field Descriptions (continued)
Bit Field Type Reset Description
3-0
SERDESAB_RXBC
LK_INV_ENA
R/W Fh
register to invert SerdesAB SRX1, SRX2, SRX3 and SRX4
rxbclks (0 -no inversion, 1 - invert)
[3] = SRX4 rxbclk invert
[2] = SRX3 rxbclk invert
[1] = SRX2 rxbclk invert
[0] = SRX1 rxbclk invert
2.3.4 Register 25h (offset = 25h) [reset = FFh]
Figure 2-45. Register 25h
7 6 5 4 3 2 1 0
SERDESCD_TXBCLK_INV_ENA SERDESAB_TXBCLK_INV_ENA
R/W-Fh R/W-Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-48. Register 25 Field Descriptions
Bit Field Type Reset Description
7-4
SERDESCD_TXBC
LK_INV_ENA
R/W Fh
register to invert SerdesCD STX5, STX6, STX7 and STX8
txbclks (0 -no inversion, 1 - invert)
[3] = STX8 txbclk invert
[2] = STX7 txbclk invert
[1] = STX6 txbclk invert
[0] = STX5 txbclk invert
3-0
SERDESAB_TXBC
LK_INV_ENA
R/W Fh
register to invert SerdesAB STX1, STX2, STX3 and STX4
txbclks (0 -no inversion, 1 - invert)
[3] = STX4 txbclk invert
[2] = STX3 txbclk invert
[1] = STX2 txbclk invert
[0] = STX1 txbclk invert
2.3.5 Register 26h (offset = 26h) [reset = FFh]
Figure 2-46. Register 26h
7 6 5 4 3 2 1 0
SERDESCD_RXBCLK_ENA SERDESAB_RXBCLK_ENA
R/W-Fh R/W-Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-49. Register 26 Field Descriptions
Bit Field Type Reset Description
7-4
SERDESCD_RXB
CLK_ENA
R/W Fh
register to enable SerdesCD SRX5, SRX6, SRX7 and SRX8
rxbclks (0 -disable, 1 - enable)
[3] = SRX8 rxbclk enable
[2] = SRX7 rxbclk enable
[1] = SRX6 rxbclk enable
[0] = SRX5 rxbclk enable
3-0
SERDESAB_RXBC
LK_ENA
R/W Fh
register to enable SerdesAB SRX1, SRX2, SRX3 and SRX4
rxbclks (0 -disable, 1 - enable)
[3] = SRX4 rxbclk enable
[2] = SRX3 rxbclk enable
[1] = SRX2 rxbclk enable
[0] = SRX1 rxbclk enable
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