Texas Instruments AFE79 Series - 2.5.52 Register 60 h (offset = 60 h) [reset = 0 h]; 2.5.53 Register 61 h (offset = 61 h) [reset = 0 h]; 2.5.54 Register 62 h (offset = 62 h) [reset = 0 h]; 2.5.55 Register 63 h (offset = 63 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.52 Register 60h (offset = 60h) [reset = 0h]
Figure 2-548. Register 60h
7 6 5 4 3 2 1 0
CFG_RX_LFSR_SEED_VAL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-553. Register 60 Field Descriptions
Bit Field Type Reset Description
7-0
CFG_RX_LFSR_S
EED_VAL[7:0]
R/W 0h
When cfg_rx_lfsr_load is 1, this spi value is used as LFSR
seed for all rx M/N dividers
2.5.53 Register 61h (offset = 61h) [reset = 0h]
Figure 2-549. Register 61h
7 6 5 4 3 2 1 0
CFG_RX_LFSR_SEED_VAL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-554. Register 61 Field Descriptions
Bit Field Type Reset Description
7-0
CFG_RX_LFSR_S
EED_VAL[15:8]
R/W 0h
When cfg_rx_lfsr_load is 1, this spi value is used as LFSR
seed for all rx M/N dividers
2.5.54 Register 62h (offset = 62h) [reset = 0h]
Figure 2-550. Register 62h
7 6 5 4 3 2 1 0
CFG_RX_LFSR_SEED_VAL[23:16]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-555. Register 62 Field Descriptions
Bit Field Type Reset Description
7-0
CFG_RX_LFSR_S
EED_VAL[23:16]
R/W 0h
When cfg_rx_lfsr_load is 1, this spi value is used as LFSR
seed for all rx M/N dividers
2.5.55 Register 63h (offset = 63h) [reset = 0h]
Figure 2-551. Register 63h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 CFG_RX_LFS
R_LOAD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset