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943
SBAU337–May 2020
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Serial Interface Register Maps
2.14.278 Register 5C0h (offset = 5C0h) [reset = 5h]
Figure 2-2161. Register 5C0h
7 6 5 4 3 2 1 0
FB_AGC_CLK_DIV_FACTOR_DVGA_CTRL[7:0]
R/W-5h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2175. Register 5C0 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_CLK_DIV
_FACTOR_DVGA_
CTRL[7:0]
R/W 5h
Clock divide factor for external DVGA control module.
This factor is used to derive the SPI clock when the device is
acting as a master to control external dvga settings. Should be
programmed such that the output clock is <25 MHz.
dvga_spi_clock = Fs/8/(clk_div_factor_dvga_ctrl+1)
2.14.279 Register 5C1h (offset = 5C1h) [reset = 0h]
Figure 2-2162. Register 5C1h
7 6 5 4 3 2 1 0
FB_AGC_CLK_DIV_FACTOR_DVGA_CTRL[10:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2176. Register 5C1 Field Descriptions
Bit Field Type Reset Description
2-0
FB_AGC_CLK_DIV
_FACTOR_DVGA_
CTRL[10:8]
R/W 0h
Clock divide factor for external DVGA control module.
This factor is used to derive the SPI clock when the device is
acting as a master to control external dvga settings. Should be
programmed such that the output clock is <25 MHz.
dvga_spi_clock = Fs/8/(clk_div_factor_dvga_ctrl+1)
2.14.280 Register 5C2h (offset = 5C2h) [reset = 0h]
Figure 2-2163. Register 5C2h
7 6 5 4 3 2 1 0
FB_AGC_SWA
P_DVGA_SPI_
ORDER
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2177. Register 5C2 Field Descriptions
Bit Field Type Reset Description
0-0
FB_AGC_SWAP_D
VGA_SPI_ORDER
R/W 0h
Controls which channel information is sent on first 6 bits of
DVGA transaction. If low information is DVGA gain of RXCHA
followed by RXCHB. If made high DVGA gain of RXCHB
followed by RXCHA
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