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Texas Instruments AFE79 Series - 2.4.54 Register 55 h (offset = 55 h) [reset = 1 h]; 2.4.55 Register 56 h (offset = 56 h) [reset = 3 h]; 2.4.56 Register 57 h (offset = 57 h) [reset = 1 Fh]; 2.4.57 Register 58 h (offset = 58 h) [reset = 1 h]

Texas Instruments AFE79 Series
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DAC JESD Register Map
283
SBAU337May 2020
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Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.4.54 Register 55h (offset = 55h) [reset = 1h]
Figure 2-283. Register 55h
7 6 5 4 3 2 1 0
LINK1_SCR LINK1_ILA_L_M1
R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-287. Register 55 Field Descriptions
Bit Field Type Reset Description
7-7 LINK1_SCR R/W 0h Turns on the scrambler when asserted
4-0 LINK1_ILA_L_M1 R/W 1h
JESD L-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
2.4.55 Register 56h (offset = 56h) [reset = 3h]
Figure 2-284. Register 56h
7 6 5 4 3 2 1 0
LINK1_ILA_F_M1
R/W-3h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-288. Register 56 Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_ILA_F_M1 R/W 3h
JESD F-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
2.4.56 Register 57h (offset = 57h) [reset = 1Fh]
Figure 2-285. Register 57h
7 6 5 4 3 2 1 0
LINK1_ILA_K_M1
R/W-1Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-289. Register 57 Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_ILA_K_M1 R/W 1Fh
JESD K-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
2.4.57 Register 58h (offset = 58h) [reset = 1h]
Figure 2-286. Register 58h
7 6 5 4 3 2 1 0
LINK1_ILA_M_M1
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

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