Texas Instruments AFE79 Series - 2.12.11 Register 66 h (offset = 66 h) [reset = 0 h]; 2.12.12 Register 68 h (offset = 68 h) [reset = 4 h]; 2.12.13 Register 69 h (offset = 69 h) [reset = 0 h]

TX Top Register Map www.ti.com
634
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.12.11 Register 66h (offset = 66h) [reset = 0h]
Figure 2-1214. Register 66h
7 6 5 4 3 2 1 0
TX_DUC_FIFO_CONFIG2
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1226. Register 66 Field Descriptions
Bit Field Type Reset Description
2-0
TX_DUC_FIFO_C
ONFIG2
R/W 0h
TX DUC FIFO Configuration2. Value dependent on
interplation factor, DAC rate, etc.
Optimal value automatically determined if System
Configuration Macros are used.
2.12.12 Register 68h (offset = 68h) [reset = 4h]
Figure 2-1215. Register 68h
7 6 5 4 3 2 1 0
TX_DUC_FIFO_CONFIG3
R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1227. Register 68 Field Descriptions
Bit Field Type Reset Description
2-0
TX_DUC_FIFO_C
ONFIG3
R/W 4h
TX DUC FIFO Configuration3. Value dependent on
interplation factor, DAC rate, etc.
Optimal value automatically determined if System
Configuration Macros are used.
2.12.13 Register 69h (offset = 69h) [reset = 0h]
Figure 2-1216. Register 69h
7 6 5 4 3 2 1 0
TX_DUC_FIFO_CONFIG4
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1228. Register 69 Field Descriptions
Bit Field Type Reset Description
2-0
TX_DUC_FIFO_C
ONFIG4
R/W 0h
TX DUC FIFO Configuration4. Value dependent on
interplation factor, DAC rate, etc.
Optimal value automatically determined if System
Configuration Macros are used.