Texas Instruments AFE79 Series - 2.6.142 Register 49 F2 h (offset = 49 F2 h) [reset = 80 h]; 2.6.143 Register 49 F3 h (offset = 49 F3 h) [reset = AAh]; 2.6.144 Register 49 F6 h (offset = 49 F6 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-861. Register 49F1 Field Descriptions (continued)
Bit Field Type Reset Description
1-1
PU_RX_INTP_LAN
E2
R/W 1h
Power up RX Lane 2 interpolator.
0h: Power down
1h: Power up
2.6.142 Register 49F2h (offset = 49F2h) [reset = 80h]
Figure 2-856. Register 49F2h
7 6 5 4 3 2 1 0
PU_RX_ADC_L
ANE3
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-862. Register 49F2 Field Descriptions
Bit Field Type Reset Description
7-7
PU_RX_ADC_LAN
E3
R/W 1h
Power up RX Lane 3 ADC.
0h: Power down
1h: Power up
2.6.143 Register 49F3h (offset = 49F3h) [reset = AAh]
Figure 2-857. Register 49F3h
7 6 5 4 3 2 1 0
PU_RX_ADC_
MASTER
PU_RX_ADC_L
ANE0
PU_RX_ADC_L
ANE1
PU_RX_ADC_L
ANE2
R/W-1h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-863. Register 49F3 Field Descriptions
Bit Field Type Reset Description
7-7
PU_RX_ADC_MAS
TER
R/W 1h
Power up RX ADC master.
0h: Power down
1h: Power up
5-5
PU_RX_ADC_LAN
E0
R/W 1h
Power up RX Lane 0 ADC.
0h: Power down
1h: Power up
3-3
PU_RX_ADC_LAN
E1
R/W 1h
Power up RX Lane 1 ADC.
0h: Power down
1h: Power up
1-1
PU_RX_ADC_LAN
E2
R/W 1h
Power up RX Lane 2 ADC.
0h: Power down
1h: Power up
2.6.144 Register 49F6h (offset = 49F6h) [reset = 0h]
Figure 2-858. Register 49F6h
7 6 5 4 3 2 1 0
REFCLK_SRC
_SEL
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset