Texas Instruments AFE79 Series - 2.6.79 Register 40 ADh (offset = 40 ADh) [reset = 0 h]; 2.6.80 Register 4140 h (offset = 4140 h) [reset = 0 h]; 2.6.81 Register 4141 h (offset = 4141 h) [reset = 40 h]

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Serial Interface Register Maps
2.6.79 Register 40ADh (offset = 40ADh) [reset = 0h]
Figure 2-793. Register 40ADh
7 6 5 4 3 2 1 0
READ_RX_FREQ_ERROR[10:8]
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-799. Register 40AD Field Descriptions
Bit Field Type Reset Description
2-0
READ_RX_FREQ_
ERROR[10:8]
R 0h
Read value of the RX frequency accumulator of format
S11.11. Each bit represents ~0.5ppm offset error between the
incoming traffic and the PLL.
2.6.80 Register 4140h (offset = 4140h) [reset = 0h]
Figure 2-794. Register 4140h
7 6 5 4 3 2 1 0
TX_SPEED_SEL TX_POLARITY
_FLIP
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-800. Register 4140 Field Descriptions
Bit Field Type Reset Description
6-4 TX_SPEED_SEL R/W 0h
TX speed select
0h: Full-rate
4h: Half-rate
5h: Quarter-rate
6h: Eighth-rate
7h: Sixteenth-rate
0-0
TX_POLARITY_FLI
P
R/W 0h
Polarity of the outgoing TX (user) data.
1h: Normal
0h: Inverted
2.6.81 Register 4141h (offset = 4141h) [reset = 40h]
Figure 2-795. Register 4141h
7 6 5 4 3 2 1 0
TX_TEST_DAT
A_SOURCE
TX_PRBS_CL
OCK_EN
TX_TEST_EN LOOPBACK_C
LOCK_INV
TX_PRBS_GE
N_EN
TX_PRBS_GE
N_ERR
TX_PRBS_MODE
R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-801. Register 4141 Field Descriptions
Bit Field Type Reset Description
7-7
TX_TEST_DATA_
SOURCE
R/W 0h
Mux control bit selecting the TX test pattern when operating in
test mode.
0h: Test pattern memory
1h: PRBS generator
6-6
TX_PRBS_CLOCK
_EN
R/W 1h
Enables the clock source to the PRBS generator.
0h: Disabled
1h: Enabled