Texas Instruments AFE79 Series - 2.6.127 Register 49 E2 h (offset = 49 E2 h) [reset = 0 h]; 2.6.128 Register 49 E3 h (offset = 49 E3 h) [reset = F0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-846. Register 49E1 Field Descriptions (continued)
Bit Field Type Reset Description
4-0
OW_FREQ_ACC_
TOP[11:7]
R/W 0h
2.6.127 Register 49E2h (offset = 49E2h) [reset = 0h]
Figure 2-841. Register 49E2h
7 6 5 4 3 2 1 0
VTSTPGROUP_TX[3:0] ENTTSTPGRO
UP_TX
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-847. Register 49E2 Field Descriptions
Bit Field Type Reset Description
7-4
VTSTPGROUP_TX
[3:0]
R/W 0h
3-3
ENTTSTPGROUP_
TX
R/W 0h
2.6.128 Register 49E3h (offset = 49E3h) [reset = F0h]
Figure 2-842. Register 49E3h
7 6 5 4 3 2 1 0
PU_TX_DRV_L
ANE0
PU_TX_DRV_L
ANE1
PU_TX_DRV_L
ANE2
PU_TX_DRV_L
ANE3
TEST_MODE_TX VTSTPGROUP
_TX[4]
R/W-1h R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-848. Register 49E3 Field Descriptions
Bit Field Type Reset Description
7-7
PU_TX_DRV_LAN
E0
R/W 1h
Power up Lane 0 TX driver.
0h: Power down
1h: Power up
6-6
PU_TX_DRV_LAN
E1
R/W 1h
Power up Lane 1 TX driver.
0h: Power down
1h: Power up
5-5
PU_TX_DRV_LAN
E2
R/W 1h
Power up Lane 2 TX driver.
0h: Power down
1h: Power up
4-4
PU_TX_DRV_LAN
E3
R/W 1h
Power up Lane 3 TX driver.
0h: Power down
1h: Power up
3-1 TEST_MODE_TX R/W 0h Analog test mux select bits. For Serdes debug only.
0-0
VTSTPGROUP_TX
[4]
R/W 0h