Texas Instruments AFE79 Series - 2.5.43 Register 51 h (offset = 51 h) [reset = 0 h]; 2.5.44 Register 54 h (offset = 54 h) [reset = 51 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.43 Register 51h (offset = 51h) [reset = 0h]
Figure 2-539. Register 51h
7 6 5 4 3 2 1 0
0 0 0 JESD_CLK_FB_DIV_N_M1
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-544. Register 51 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
JESD_CLK_FB_DI
V_N_M1
R/W 0h
N-1 value of jesd divider.
Output of this divider, clock frequency should match STX
3,4/7,8 rates i.e. lane _rate/40 or lane_rate/33
2.5.44 Register 54h (offset = 54h) [reset = 51h]
Figure 2-540. Register 54h
7 6 5 4 3 2 1 0
CTRL_RX2_ROOT_CLK_P2 CTRL_RX2_ROOT_CLK_P0 CTRL_RX1_ROOT_CLK_P2 CTRL_RX1_ROOT_CLK_P0
R/W-1h R/W-1h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-545. Register 54 Field Descriptions
Bit Field Type Reset Description
7-6
CTRL_RX2_ROOT
_CLK_P2
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
5-4
CTRL_RX2_ROOT
_CLK_P0
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
3-2
CTRL_RX1_ROOT
_CLK_P2
R/W 0h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
1-0
CTRL_RX1_ROOT
_CLK_P0
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled