Texas Instruments AFE79 Series - 2.13.312 Register 54 Ch (offset = 54 Ch) [reset = 0 h]; 2.13.313 Register 54 Dh (offset = 54 Dh) [reset = 0 h]; 2.13.314 Register 54 Eh (offset = 54 Eh) [reset = 0 h]; 2.13.315 Register 54 Fh (offset = 54 Fh) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.13.312 Register 54Ch (offset = 54Ch) [reset = 0h]
Figure 2-1724. Register 54Ch
7 6 5 4 3 2 1 0
RX_AGC_BAND0_LNA_PHASE8[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1737. Register 54C Field Descriptions
Bit Field Type Reset Description
7-0
RX_AGC_BAND0_
LNA_PHASE8[7:0]
R/W 0h
LNA Phase for Band0 for temp index 8 in case of External
LNA Control , Phase for DVGA Index 8 in case of External
DVGA control
2.13.313 Register 54Dh (offset = 54Dh) [reset = 0h]
Figure 2-1725. Register 54Dh
7 6 5 4 3 2 1 0
RX_AGC_BAND0_LNA_PHASE
8[9:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1738. Register 54D Field Descriptions
Bit Field Type Reset Description
1-0
RX_AGC_BAND0_
LNA_PHASE8[9:8]
R/W 0h
LNA Phase for Band0 for temp index 8 in case of External
LNA Control , Phase for DVGA Index 8 in case of External
DVGA control
2.13.314 Register 54Eh (offset = 54Eh) [reset = 0h]
Figure 2-1726. Register 54Eh
7 6 5 4 3 2 1 0
RX_AGC_BAND0_LNA_PHASE9[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1739. Register 54E Field Descriptions
Bit Field Type Reset Description
7-0
RX_AGC_BAND0_
LNA_PHASE9[7:0]
R/W 0h
LNA Phase for Band0 for temp index 9 in case of External
LNA Control , Phase for DVGA Index 9 in case of External
DVGA control
2.13.315 Register 54Fh (offset = 54Fh) [reset = 0h]
Figure 2-1727. Register 54Fh
7 6 5 4 3 2 1 0
RX_AGC_BAND0_LNA_PHASE
9[9:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset