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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-1963. Register 404 Field Descriptions
Bit Field Type Reset Description
6-6 reserved R/W 0h
5-5
FB_AGC_PWR_D
ECAY_DET_EN
R/W 0h
Power decay detector enable
0 : Disable
1 : Enable
4-4
FB_AGC_PWR_AT
TACK_DET_EN
R/W 0h
Power attack detetcor enable
0 : Disable
1 : Enable
3-3
FB_AGC_SMALL_
STEP_DECAY_DE
T_EN
R/W 1h
Small step decay detector enable
0 : Disable
1 : Enable
2-2
FB_AGC_BIG_STE
P_DECAY_DET_E
N
R/W 0h
Big step decay detector enable
0 : Disable
1 : Enable
1-1
FB_AGC_SMALL_
STEP_ATTACK_D
ET_EN
R/W 1h
Small step attack detector enable
0 : Disable
1 : Enable
0-0
FB_AGC_BIG_STE
P_ATTACK_DET_
EN
R/W 0h
Big step attack detector enable
0 : Disable
1 : Enable
2.14.67 Register 405h (offset = 405h) [reset = 0h]
Figure 2-1950. Register 405h
7 6 5 4 3 2 1 0
FB_AGC_LNA_
RF_ATTACK_D
ET_EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1964. Register 405 Field Descriptions
Bit Field Type Reset Description
0-0
FB_AGC_LNA_RF
_ATTACK_DET_E
N
R/W 0h
LNA RF attack detector enable
0 : Disable
1 : Enable
2.14.68 Register 408h (offset = 408h) [reset = 6h]
Figure 2-1951. Register 408h
7 6 5 4 3 2 1 0
FB_AGC_BIG_STEP_ATTACK_STEP_SIZE
R/W-6h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1965. Register 408 Field Descriptions
Bit Field Type Reset Description
5-0
FB_AGC_BIG_STE
P_ATTACK_STEP
_SIZE
R/W 6h
Gain step when Digital big step attack is triggered. 0.5 dB step
size.