Texas Instruments AFE79 Series - 2.5.34 Register 48 h (offset = 48 h) [reset = 1 h]; 2.5.35 Register 49 h (offset = 49 h) [reset = 0 h]; 2.5.36 Register 4 Ah (offset = 4 Ah) [reset = 1 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.34 Register 48h (offset = 48h) [reset = 1h]
Figure 2-530. Register 48h
7 6 5 4 3 2 1 0
0 0 0 DDC_RD_CLK_RX2_DIV_M
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-535. Register 48 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
DDC_RD_CLK_RX
2_DIV_M
R/W 1h
M value of ddc divider.
Output of this divider, clock frequency should match the
RXB/RXD interface rate
2.5.35 Register 49h (offset = 49h) [reset = 0h]
Figure 2-531. Register 49h
7 6 5 4 3 2 1 0
0 0 0 DDC_RD_CLK_RX2_DIV_N_M1
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-536. Register 49 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
DDC_RD_CLK_RX
2_DIV_N_M1
R/W 0h
N-1 value of ddc divider.
Output of this divider, clock frequency should match the
RXB/RXD interface rate
2.5.36 Register 4Ah (offset = 4Ah) [reset = 1h]
Figure 2-532. Register 4Ah
7 6 5 4 3 2 1 0
0 0 0 DDC_RD_CLK_FB_DIV_M
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-537. Register 4A Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
DDC_RD_CLK_FB
_DIV_M
R/W 1h
M value of ddc divider.
Output of this divider, clock frequency should match the
FBAB/FBCD interface rate