Texas Instruments AFE79 Series - 2.4.64 Register 5 Fh (offset = 5 Fh) [reset = 0 h]; 2.4.65 Register 60 h (offset = 60 h) [reset = 0 h]; 2.4.66 Register 61 h (offset = 61 h) [reset = 1 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.4.64 Register 5Fh (offset = 5Fh) [reset = 0h]
Figure 2-293. Register 5Fh
7 6 5 4 3 2 1 0
LINK1_ILA_CO
NFIG_OVERRI
DE
LINK1_CTRL_
CONFIG_OVE
RRIDE
LINK0_ILA_CO
NFIG_OVERRI
DE
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-297. Register 5F Field Descriptions
Bit Field Type Reset Description
7-7
LINK1_ILA_CONFI
G_OVERRIDE
R/W 0h
By default, ILA values(only L,M,F,S,Hd,K,N,N') are set by
jesd_mode. Set this bit to override the Link1 ILA values with
register based ILA values for
6-6
LINK1_CTRL_CON
FIG_OVERRIDE
R/W 0h TESTMODE
5-5
LINK0_ILA_CONFI
G_OVERRIDE
R/W 0h
By default, ILA values(only L,M,F,S,Hd,K,N,N') are set by
jesd_mode. Set this bit to override the Link0 ILA values with
register based ILA values for
2.4.65 Register 60h (offset = 60h) [reset = 0h]
Figure 2-294. Register 60h
7 6 5 4 3 2 1 0
LID0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-298. Register 60 Field Descriptions
Bit Field Type Reset Description
4-0 LID0 R/W 0h JESD Lane ID for lane0/4
2.4.66 Register 61h (offset = 61h) [reset = 1h]
Figure 2-295. Register 61h
7 6 5 4 3 2 1 0
LID1
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-299. Register 61 Field Descriptions
Bit Field Type Reset Description
4-0 LID1 R/W 1h JESD Lane ID for lane1/5