Texas Instruments AFE79 Series - 2.15.30 Register A4 h (offset = A4 h) [reset = 0 h]; 2.15.31 Register A5 h (offset = A5 h) [reset = 0 h]; 2.15.32 Register A6 h (offset = A6 h) [reset = 0 h]; 2.15.33 Register A7 h (offset = A7 h) [reset = 0 h]

www.ti.com Timing Controller Register Map
969
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.15.30 Register A4h (offset = A4h) [reset = 0h]
Figure 2-2237. Register A4h
7 6 5 4 3 2 1 0
ENABLE_RX_GAIN_SWAP_A
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2252. Register A4 Field Descriptions
Bit Field Type Reset Description
1-0
ENABLE_RX_GAI
N_SWAP_A
R/W 0h
Acts as an EN for rxgswap for each bit of chA. If a bit of the
enable is 0, then the corresponding gain_swap bit will be
always 0.
2.15.31 Register A5h (offset = A5h) [reset = 0h]
Figure 2-2238. Register A5h
7 6 5 4 3 2 1 0
ENABLE_RX_GAIN_SWAP_B
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2253. Register A5 Field Descriptions
Bit Field Type Reset Description
1-0
ENABLE_RX_GAI
N_SWAP_B
R/W 0h
Acts as an EN for rxgswap for each bit of chB. If a bit of the
enable is 0, then the corresponding gain_swap bit will be
always 0.
2.15.32 Register A6h (offset = A6h) [reset = 0h]
Figure 2-2239. Register A6h
7 6 5 4 3 2 1 0
ENABLE_RX_GAIN_SWAP_C
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2254. Register A6 Field Descriptions
Bit Field Type Reset Description
1-0
ENABLE_RX_GAI
N_SWAP_C
R/W 0h
Acts as an EN for rxgswap for each bit of chC. If a bit of the
enable is 0, then the corresponding gain_swap bit will be
always 0.
2.15.33 Register A7h (offset = A7h) [reset = 0h]
Figure 2-2240. Register A7h
7 6 5 4 3 2 1 0
ENABLE_RX_GAIN_SWAP_D
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset