Texas Instruments AFE79 Series - 2.4.44 Register 4 Bh (offset = 4 Bh) [reset = Fh]; 2.4.45 Register 4 Ch (offset = 4 Ch) [reset = 2 Fh]; 2.4.46 Register 4 Dh (offset = 4 Dh) [reset = 20 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.4.44 Register 4Bh (offset = 4Bh) [reset = Fh]
Figure 2-273. Register 4Bh
7 6 5 4 3 2 1 0
LINK0_CS LINK0_ILA_N_M1
R/W-0h R/W-Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-277. Register 4B Field Descriptions
Bit Field Type Reset Description
7-6 LINK0_CS R/W 0h Lane configuration
4-0 LINK0_ILA_N_M1 R/W Fh
JESD N-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
2.4.45 Register 4Ch (offset = 4Ch) [reset = 2Fh]
Figure 2-274. Register 4Ch
7 6 5 4 3 2 1 0
LINK0_SUBCLASSV LINK0_ILA_NPRIME_M1
R/W-1h R/W-Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-278. Register 4C Field Descriptions
Bit Field Type Reset Description
7-5
LINK0_SUBCLASS
V
R/W 1h
Selects the JESD subclass. Note: '1' is subclass 1 and '0' is
subclass 0; they are the only modes supported; not used for
operation but used for configuration. See min_latency_ena for
use in subclass 0
4-0
LINK0_ILA_NPRIM
E_M1
R/W Fh
JESD N'-1 configuration value used only for ILA checking;
may be set independently of the actual JESD mode
2.4.46 Register 4Dh (offset = 4Dh) [reset = 20h]
Figure 2-275. Register 4Dh
7 6 5 4 3 2 1 0
LINK0_JESDV LINK0_ILA_S_M1
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-279. Register 4D Field Descriptions
Bit Field Type Reset Description
7-5 LINK0_JESDV R/W 1h
Selects the version of JESD support
0=A
1=B
2=C
4-0 LINK0_ILA_S_M1 R/W 0h
JESD S-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode