DAC JESD Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.4.220 Register 115h (offset = 115h) [reset = 0h]
Figure 2-449. Register 115h
7 6 5 4 3 2 1 0
ALARMS_TO_PAP_CLEAR[47:40]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-453. Register 115 Field Descriptions
Bit Field Type Reset Description
7-0
ALARMS_TO_PAP
_CLEAR[47:40]
R/W 0h
Clear 'alarms_to_pap' register to the pap-alarms; Alarms won't
be generated if '1' so it must be programmed to '0' for alarms
to continue.
[47:40] = SRX2/6 JESD errors
Each of the bits for the above mentioned lane errors are
mapped to :
bit7 = JESDB: multiframe alignment error
bit6 = JESDB: frame alignment error
bit5 = JESDB: link configuration error
bit4 = JESDB: elastic buffer overflow (bad RBD value)
bit3 = JESDB: elastic buffer match error. The first non-/K/
doesnt match 'match_ctrl' and 'match_data' programmed
values
bit2 = JESDB: code synchronization error
bit1 = JESDB: 8b/10b not-in-table code error
Bit0 = JESDB: 8b/10b disparity error
bit7 = JESDC: EoEMB alignment error
bit6 = JESDC: EoMB alignment error
bit5 = JESDC: cmd-data in crc mode not matching with spi
register bits
bit4 = JESDC: elastic buffer overflow (bad RBD value)
bit3 = JESDC: TIED to 0.
bit2 = JESDC: extended multiblock alignment error
bit1 = JESDC: sync-header invalid error ('11' or '00' received
in expected sync header location)
Bit0 = JESDC: sync-header CRC error
Note: Refer to the TI application note for details on error
interpretation.
2.4.221 Register 116h (offset = 116h) [reset = 0h]
Figure 2-450. Register 116h
7 6 5 4 3 2 1 0
ALARMS_TO_PAP_CLEAR[55:48]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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