JESD_SUBCHIP Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-173. Register D4 Field Descriptions (continued)
Bit Field Type Reset Description
4-4
IQ_SWAP_TXC_B
0
R/W 0h
When 1, swap iq data of TXC_B0
Used for IQ swap
0 : No swap
1 : swap
3-3
IQ_SWAP_TXB_B
1
R/W 0h
When 1, swap iq data of TXB_B1
Used for IQ swap
0 : No swap
1 : swap
2-2
IQ_SWAP_TXB_B
0
R/W 0h
When 1, swap iq data of TXB_B0
Used for IQ swap
0 : No swap
1 : swap
1-1
IQ_SWAP_TXA_B
1
R/W 0h
When 1, swap iq data of TXA_B1
Used for IQ swap
0 : No swap
1 : swap
0-0
IQ_SWAP_TXA_B
0
R/W 0h
When 1, swap iq data of TXA_B0
Used for IQ swap
0 : No swap
1 : swap
2.3.130 Register 155h (offset = 155h) [reset = 0h]
Figure 2-171. Register 155h
7 6 5 4 3 2 1 0
TXD_DAC_CL
K_EN_OVR
TXC_DAC_CL
K_EN_OVR
TXB_DAC_CLK
_EN_OVR
TXA_DAC_CLK
_EN_OVR
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-174. Register 155 Field Descriptions
Bit Field Type Reset Description
7-7
TXD_DAC_CLK_E
N_OVR
R/W 0h
Register to gate the TXD clocks used internally and going to
TX_TOP. Need to be used along with 'txd_dac_clk_en_val'
register
6-6
TXC_DAC_CLK_E
N_OVR
R/W 0h
Register to gate the TXC clocks used internally and going to
TX_TOP. Need to be used along with 'txc_dac_clk_en_val'
register
5-5
TXB_DAC_CLK_E
N_OVR
R/W 0h
Register to gate the TXB clocks used internally and going to
TX_TOP. Need to be used along with 'txb_dac_clk_en_val'
register
4-4
TXA_DAC_CLK_E
N_OVR
R/W 0h
Register to gate the TXA clocks used internally and going to
TX_TOP. Need to be used along with 'txa_dac_clk_en_val'
register
2.3.131 Register 156h (offset = 156h) [reset = FFh]
Figure 2-172. Register 156h
7 6 5 4 3 2 1 0
TXB_DAC_CLK_EN_VAL TXA_DAC_CLK_EN_VAL
R/W-Fh R/W-Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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