Texas Instruments AFE79 Series - 2.6.97 Register 41 FAh (offset = 41 FAh) [reset = 46 h]; 2.6.98 Register 41 FBh (offset = 41 FBh) [reset = 0 h]; 2.6.99 Register 41 FCh (offset = 41 FCh) [reset = 84 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.6.97 Register 41FAh (offset = 41FAh) [reset = 46h]
Figure 2-811. Register 41FAh
7 6 5 4 3 2 1 0
VREF_DELAY_DAC_TOP VREF_DELAY_DAC_BOT
R/W-4h R/W-3h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-817. Register 41FA Field Descriptions
Bit Field Type Reset Description
6-4
VREF_DELAY_DA
C_TOP
R/W 4h Clock Phase Range, top
3-1
VREF_DELAY_DA
C_BOT
R/W 3h Clock Phase Range, bottom
2.6.98 Register 41FBh (offset = 41FBh) [reset = 0h]
Figure 2-812. Register 41FBh
7 6 5 4 3 2 1 0
EXRESET_INT
P
ADDCAP_CLK
PHASE
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-818. Register 41FB Field Descriptions
Bit Field Type Reset Description
5-5 EXRESET_INTP R/W 0h Reset RX Interpolator
4-4
ADDCAP_CLKPHA
SE
R/W 0h Clock Phase Edge Delay
2.6.99 Register 41FCh (offset = 41FCh) [reset = 84h]
Figure 2-813. Register 41FCh
7 6 5 4 3 2 1 0
VGAVDSAT[0] PU_RX_INTP_
LANE
R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-819. Register 41FC Field Descriptions
Bit Field Type Reset Description
7-7 VGAVDSAT[0] R/W 1h
2-2
PU_RX_INTP_LAN
E
R/W 1h
Power up RX interpolator by lane.
0h: Power down
1h: Power up