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IO Wrap Register Map
1173
SBAU337–May 2020
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Serial Interface Register Maps
2.16.526 Register 9E1h (offset = 9E1h) [reset = 2h]
Figure 2-2789. Register 9E1h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_TDD_EN_R
XD
OVR_INTPI_T
DD_EN_RXD
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2805. Register 9E1 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
TDD_EN_RXD
R/W 1h
control to select whether the input function intpi_tdd_en_rxd
needs to be overriden ot not. 1 indicates override.
0-0
OVR_INTPI_TDD_
EN_RXD
R/W 0h override value for ovr_sel_intpi_tdd_en_rxd is made high
2.16.527 Register 9E4h (offset = 9E4h) [reset = 0h]
Figure 2-2790. Register 9E4h
7 6 5 4 3 2 1 0
SEL_INTPI_RX_GAIN_SW_0 POL_INTPI_RX
_GAIN_SW_0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2806. Register 9E4 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_RX_G
AIN_SW_0
R/W 0h
select control for intpi_rx_gain_sw_0. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_RX_G
AIN_SW_0
R/W 0h
polarity control for intpi_rx_gain_sw_0. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
2.16.528 Register 9E5h (offset = 9E5h) [reset = 2h]
Figure 2-2791. Register 9E5h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_RX_GAIN_S
W_0
OVR_INTPI_R
X_GAIN_SW_0
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2807. Register 9E5 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
RX_GAIN_SW_0
R/W 1h
control to select whether the input function intpi_rx_gain_sw_0
needs to be overriden ot not. 1 indicates override.
0-0
OVR_INTPI_RX_G
AIN_SW_0
R/W 0h override value for ovr_sel_intpi_rx_gain_sw_0 is made high
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