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ADC JESD Register Map
413
SBAU337–May 2020
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Serial Interface Register Maps
2.5.80 Register 83h (offset = 83h) [reset = 0h]
Figure 2-576. Register 83h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 LINK0_JESD_I
LA_CONFIG_O
VERRIDE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-581. Register 83 Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0
LINK0_JESD_ILA_
CONFIG_OVERRI
DE
R/W 0h
Controls STX1/5
by default, JESD ILA parameters are defined from
JESD_MODE[7:0] settings when this bit is 0. mem_ila* are
dont care.
When 1, mem_link0_ila* registers are used to compute link
config
0 : Use functionally computed ILA LMFSN paramters
1 : Use ila* registers for ILA LMFSN parameters
2.5.81 Register 84h (offset = 84h) [reset = 0h]
Figure 2-577. Register 84h
7 6 5 4 3 2 1 0
LINK0_K_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-582. Register 84 Field Descriptions
Bit Field Type Reset Description
7-0 LINK0_K_M1 R/W 0h
Number of frames in a
multiframe, for STX1/5
When link0_jesd_ila_config_override is 0,
this register is used as JESD link config for STX1/5
2.5.82 Register 85h (offset = 85h) [reset = 0h]
Figure 2-578. Register 85h
7 6 5 4 3 2 1 0
0 0 0 0 LINK0_ENABL
E_F_CHAR_O
N_MFEND
LINK0_DISABL
E_F_CHAR
LINK0_DISABL
E_A_CHAR
LINK0_NO_LA
NE_SYNC
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-583. Register 85 Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-3
LINK0_ENABLE_F
_CHAR_ON_MFE
ND
R/W 0h
Config for STX1/5
By default, don't send f_char on multiframe_end.
When 1, f_char is sen't on multiframe_end
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