Texas Instruments AFE79 Series - 2.14.322 Register 771 h (offset = 771 h) [reset = 0 h]; 2.14.323 Register 772 h (offset = 772 h) [reset = 0 h]; 2.14.324 Register 773 h (offset = 773 h) [reset = 1 h]

FB Top Register Map www.ti.com
958
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.14.322 Register 771h (offset = 771h) [reset = 0h]
Figure 2-2205. Register 771h
7 6 5 4 3 2 1 0
FB_DDC_PRE
_DECIM_PDN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2219. Register 771 Field Descriptions
Bit Field Type Reset Description
0-0
FB_DDC_PRE_DE
CIM_PDN
R/W 0h
Power down the pre-decimation section of FB channel
1 : Turn off FB PDDC clock
0 : Enable FB PDDC clock
2.14.323 Register 772h (offset = 772h) [reset = 0h]
Figure 2-2206. Register 772h
7 6 5 4 3 2 1 0
FB_DDC_DECI
M_PDN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2220. Register 772 Field Descriptions
Bit Field Type Reset Description
0-0
FB_DDC_DECIM_
PDN
R/W 0h
Power down the DDC section of FB channel
1 : Turn off FB DDC clock
0 : Enable FB DDC clock
2.14.324 Register 773h (offset = 773h) [reset = 1h]
Figure 2-2207. Register 773h
7 6 5 4 3 2 1 0
FB_AGC_PDN
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2221. Register 773 Field Descriptions
Bit Field Type Reset Description
0-0 FB_AGC_PDN R/W 1h
Power down the AGC
1 : Turn off FB AGC clock
0 : Enable FB AGC clock