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DAC JESD Register Map
313
SBAU337–May 2020
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Serial Interface Register Maps
2.4.135 Register ADh (offset = ADh) [reset = 84h]
Figure 2-364. Register ADh
7 6 5 4 3 2 1 0
EMB_ALIGN_INVALID_THRESH EMB_ALIGN_VALID_THRESH
R/W-8h R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-368. Register AD Field Descriptions
Bit Field Type Reset Description
7-4
EMB_ALIGN_INVA
LID_THRESH
R/W 8h
JESDC:Minimum number of continous invalid EoEMB blocks
needed needed to jump from lock state to init state
JESDB : UNUSED
3-0
EMB_ALIGN_VALI
D_THRESH
R/W 4h
JESDC:Minimum number of valid EoEMB blocks needed
needed to jump from hunt state to lock state
JESDB : UNUSED
2.4.136 Register AEh (offset = AEh) [reset = 0h]
Figure 2-365. Register AEh
7 6 5 4 3 2 1 0
JESDC_ENCODING_MODE JESDC_CRC_
MODE
JESDC_80B_M
ODE_EN
DATA_BITS_R
EORDER_AFT
ER_CRC
DATA_BYTES_
REORDER_AF
TER_CRC
DATA_BITS_R
EORDER_BEF
ORE_CRC
DATA_BYTES_
REORDER_BE
FORE_CRC
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-369. Register AE Field Descriptions
Bit Field Type Reset Description
7-6
JESDC_ENCODIN
G_MODE
R/W 0h
JESDC: Encoding mode
JESDB : UNUSED
0 : CRC
1 : FEC (Not used)
2 : CMD(Not used)
5-5
JESDC_CRC_MO
DE
R/W 0h
JESDC: CRC mode
JESDB : UNUSED
0 : CRC12
1 : CRC3
4-4
JESDC_80B_MOD
E_EN
R/W 0h
JESDC: sets 80b mode en
JESDB : UNUSED
0 : 66b
1 : 80b
3-3
DATA_BITS_REO
RDER_AFTER_CR
C
R/W 0h UNUSED
2-2
DATA_BYTES_RE
ORDER_AFTER_C
RC
R/W 0h UNUSED
1-1
DATA_BITS_REO
RDER_BEFORE_C
RC
R/W 0h UNUSED
0-0
DATA_BYTES_RE
ORDER_BEFORE
_CRC
R/W 0h UNUSED