Texas Instruments AFE79 Series - 2.6.136 Register 49 ECh (offset = 49 ECh) [reset = 40 h]; 2.6.137 Register 49 EDh (offset = 49 EDh) [reset = 9 Ch]; 2.6.138 Register 49 EEh (offset = 49 EEh) [reset = 0 h]

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Serial Interface Register Maps
Table 2-855. Register 49EB Field Descriptions
Bit Field Type Reset Description
7-0 TX_PLL_N R/W 14h
TX PLL clock multiplier where the PLL frequency = PLL
reference clock * 2 * PLL_N. The SerDes user rate = 2 * PLL
frequency.
2.6.136 Register 49ECh (offset = 49ECh) [reset = 40h]
Figure 2-850. Register 49ECh
7 6 5 4 3 2 1 0
TX_REFCLK_S
EL
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-856. Register 49EC Field Descriptions
Bit Field Type Reset Description
6-6 TX_REFCLK_SEL R/W 1h
Mux control to select either the reference clock or a recovered
clock for the TX PLL. See register PzF0 for recovered clock
options.
0h: Recovered clock
1h: Reference clock
2.6.137 Register 49EDh (offset = 49EDh) [reset = 9Ch]
Figure 2-851. Register 49EDh
7 6 5 4 3 2 1 0
TX_PLL_BIAS4 PU_TX_BAND
GAP
PU_RVDD_TX EN_RVDDVCO
_TX
R/W-4h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-857. Register 49ED Field Descriptions
Bit Field Type Reset Description
7-5 TX_PLL_BIAS4 R/W 4h Controls the TX PLL bias setting 4.
4-4 PU_TX_BANDGAP R/W 1h
Power up TX PLL bandgap.
0h: Power down
1h: Power up
3-3 PU_RVDD_TX R/W 1h
2-2 EN_RVDDVCO_TX R/W 1h
2.6.138 Register 49EEh (offset = 49EEh) [reset = 0h]
Figure 2-852. Register 49EEh
7 6 5 4 3 2 1 0
TEST_MUX_S
EL_B[0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset