Texas Instruments AFE79 Series - 2.4.128 Register A2 h (offset = A2 h) [reset = 0 h]; 2.4.129 Register A3 h (offset = A3 h) [reset = 0 h]; 2.4.130 Register A4 h (offset = A4 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.4.128 Register A2h (offset = A2h) [reset = 0h]
Figure 2-357. Register A2h
7 6 5 4 3 2 1 0
JESD_CS_STATE
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-361. Register A2 Field Descriptions
Bit Field Type Reset Description
7-0 JESD_CS_STATE R 0h
JESDB: CS_STATE value
JESDC: EMB_STATE value
bits(1:0) = SRX1/5
bits(3:2) = SRX2/6
bits(5:4) = SRX3/7
bits(7:6) = SRX4/8
For stable link, the bits for each lane enabled should read as
"10"
Note: Refer to the TI application note for details on error
interpretation.
2.4.129 Register A3h (offset = A3h) [reset = 0h]
Figure 2-358. Register A3h
7 6 5 4 3 2 1 0
JESD_CS_STATE_PREV
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-362. Register A3 Field Descriptions
Bit Field Type Reset Description
7-0
JESD_CS_STATE
_PREV
R 0h
JESDB: Previous CS_STATE value
JESDC: Previous EMB_STATE value
bits(1:0) = SRX1/5
bits(3:2) = SRX2/6
bits(5:4) = SRX3/7
bits(7:6) = SRX4/8
For stable link, the bits for each lane enabled should read as
"01"
Note: Refer to the TI application note for details on error
interpretation.
2.4.130 Register A4h (offset = A4h) [reset = 0h]
Figure 2-359. Register A4h
7 6 5 4 3 2 1 0
JESD_FS_STATE
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset