Texas Instruments AFE79 Series - 2.3.61 Register 6 Dh (offset = 6 Dh) [reset = 32 h]; 2.3.62 Register 6 Eh (offset = 6 Eh) [reset = 54 h]

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Serial Interface Register Maps
2.3.61 Register 6Dh (offset = 6Dh) [reset = 32h]
Figure 2-102. Register 6Dh
7 6 5 4 3 2 1 0
RXOCTETPATH3_CLK_SEL RXOCTETPATH2_CLK_SEL
R/W-3h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-105. Register 6D Field Descriptions
Bit Field Type Reset Description
6-4
RXOCTETPATH3_
CLK_SEL
R/W 3h
Selects the input SERDES-Rx lane clk for data that is
normally supposed to be on SRX4.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2-0
RXOCTETPATH2_
CLK_SEL
R/W 2h
Selects the input SERDES-Rx lane clk for data that is
normally supposed to be on SRX3.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2.3.62 Register 6Eh (offset = 6Eh) [reset = 54h]
Figure 2-103. Register 6Eh
7 6 5 4 3 2 1 0
RXOCTETPATH5_CLK_SEL RXOCTETPATH4_CLK_SEL
R/W-5h R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-106. Register 6E Field Descriptions
Bit Field Type Reset Description
6-4
RXOCTETPATH5_
CLK_SEL
R/W 5h
Selects the input SERDES-Rx lane clk for data that is
normally supposed to be on SRX6.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2-0
RXOCTETPATH4_
CLK_SEL
R/W 4h
Selects the input SERDES-Rx lane clk for data that is
normally supposed to be on SRX5.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk