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DAC JESD Register Map
325
SBAU337–May 2020
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Serial Interface Register Maps
2.4.173 Register D5h (offset = D5h) [reset = 0h]
Figure 2-402. Register D5h
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT14[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-406. Register D5 Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT14[15:8]
R/W 0h short test pattern input
2.4.174 Register D6h (offset = D6h) [reset = 0h]
Figure 2-403. Register D6h
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT15[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-407. Register D6 Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT15[7:0]
R/W 0h short test pattern input
2.4.175 Register D7h (offset = D7h) [reset = 0h]
Figure 2-404. Register D7h
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT15[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-408. Register D7 Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT15[15:8]
R/W 0h short test pattern input
2.4.176 Register E8h (offset = E8h) [reset = 0h]
Figure 2-405. Register E8h
7 6 5 4 3 2 1 0
CLEAR_EMB_ALIGN_LOCK_FLAG CLEAR_COMMA_ALIGN_LOCK_FLAG
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset