Texas Instruments AFE79 Series - 2.4.186 Register F2 h (offset = F2 h) [reset = 0 h]; 2.4.187 Register F3 h (offset = F3 h) [reset = 0 h]; 2.4.188 Register F4 h (offset = F4 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.4.186 Register F2h (offset = F2h) [reset = 0h]
Figure 2-415. Register F2h
7 6 5 4 3 2 1 0
JESD_SYSREF_DIV2_TX1_FLAG JESD_CLK_DIV2_TX1_FLAG
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-419. Register F2 Field Descriptions
Bit Field Type Reset Description
7-4
JESD_SYSREF_DI
V2_TX1_FLAG
R 0h jesd_rx_div2_sysref monitor flag
3-0
JESD_CLK_DIV2_
TX1_FLAG
R 0h jesd_rx_div2_clk monitor flag
2.4.187 Register F3h (offset = F3h) [reset = 0h]
Figure 2-416. Register F3h
7 6 5 4 3 2 1 0
DUC_SYSREF_TX1_FLAG DUC_CLK_TX1_FLAG
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-420. Register F3 Field Descriptions
Bit Field Type Reset Description
7-4
DUC_SYSREF_TX
1_FLAG
R 0h duc_wr_sysref monitor flag
3-0
DUC_CLK_TX1_FL
AG
R 0h duc_wr_clk monitor flag
2.4.188 Register F4h (offset = F4h) [reset = 0h]
Figure 2-417. Register F4h
7 6 5 4 3 2 1 0
JESD_SYSREF_TX2_FLAG JESD_CLK_TX2_FLAG
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-421. Register F4 Field Descriptions
Bit Field Type Reset Description
7-4
JESD_SYSREF_T
X2_FLAG
R 0h jesd_rx_sysref monitor flag
3-0
JESD_CLK_TX2_F
LAG
R 0h jesd_rx_clk monitor flag