ADC JESD Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-509. Register 2C Field Descriptions (continued)
Bit Field Type Reset Description
1-1
TDD_RX_FBZ_DY
N_SWITCH_OVR
R/W 0h Used when jesd_system_mode is 1/5/6/7/8
0-0
TDD_RX_FBZ_DY
N_SWITCH_VAL
R/W 0h
Used in TDD mode
When tdd_rx_fbz_dyn_switch_ovr is 1, this spi value is used in
place of dynamically switching signal generated from rx/fb_on
1 -> Send RX
0 -> Send FB
2.5.9 Register 2Eh (offset = 2Eh) [reset = 0h]
Figure 2-505. Register 2Eh
7 6 5 4 3 2 1 0
0 0 0 0 TDD_FBABZ_F
BCD_DYN_SW
ITCH_INV
TDD_FBABZ_F
BCD_DYN_SW
ITCH_OVR
TDD_FBABZ_F
BCD_DYN_SW
ITCH_VAL
TDD_FBABZ_F
BCD_DYN_SW
ITCH_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-510. Register 2E Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-3
TDD_FBABZ_FBC
D_DYN_SWITCH_I
NV
R/W 0h Polarity inversion of the switching signal fbabz_fbcd
2-2
TDD_FBABZ_FBC
D_DYN_SWITCH_
OVR
R/W 0h
When 1, the spi val is used to switch the fbabz_fbcd signal in
adc_jesd
1-1
TDD_FBABZ_FBC
D_DYN_SWITCH_
VAL
R/W 0h
After ovr is 1,
0 -> No swap in fbab/fbcd
1 -> Swap fbab/fbcd
0-0
TDD_FBABZ_FBC
D_DYN_SWITCH_
EN
R/W 0h
To enable tdd dynamic switching of fbab fbcd
0 : No FB AB and FB CD dynamic switching
1 : Enable FB AB and FB CD dynamic switching
2.5.10 Register 2Fh (offset = 2Fh) [reset = 0h]
Figure 2-506. Register 2Fh
7 6 5 4 3 2 1 0
TDD_SHARED_DATA_SEL_LAN
E3
TDD_SHARED_DATA_SEL_LAN
E2
TDD_SHARED_DATA_SEL_LAN
E1
TDD_SHARED_DATA_SEL_LAN
E0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-511. Register 2F Field Descriptions
Bit Field Type Reset Description
7-6
TDD_SHARED_DA
TA_SEL_LANE3
R/W 0h
Used to control lane 3/7 sharing for system_modes that
support TDD shared
0 - rx/fb shared dynamically
1 - rx
2 - fb
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