Texas Instruments AFE79 Series - 2.13.4 Register 43 h (offset = 43 h) [reset = 0 h]; 2.13.5 Register 44 h (offset = 44 h) [reset = 0 h]; 2.13.6 Register 48 h (offset = 48 h) [reset = 52 h]

RX Top Register Map www.ti.com
712
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-1428. Register 42 Field Descriptions
Bit Field Type Reset Description
0-0
RX_DDC_BANDS_
CONFIG
R/W 0h
Single/dual band DDC mode config.
0: Single Band;
1: Dual Band
2.13.4 Register 43h (offset = 43h) [reset = 0h]
Figure 2-1416. Register 43h
7 6 5 4 3 2 1 0
RX_DDC_BW_
CONFIG
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1429. Register 43 Field Descriptions
Bit Field Type Reset Description
0-0
RX_DDC_BW_CO
NFIG
R/W 0h
Bandwidth indication
Set this to 1 when decimation factor is < 8, (in addition to
rx_ddc_mode_config above).
2.13.5 Register 44h (offset = 44h) [reset = 0h]
Figure 2-1417. Register 44h
7 6 5 4 3 2 1 0
RX_DDC_REA
L_MODE_CON
FIG
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1430. Register 44 Field Descriptions
Bit Field Type Reset Description
0-0
RX_DDC_REAL_M
ODE_CONFIG
R/W 0h
FB DDC real output mode enable
0: Complex (I/Q) output mode (default)
1: Real (I-only) output mode
2.13.6 Register 48h (offset = 48h) [reset = 52h]
Figure 2-1418. Register 48h
7 6 5 4 3 2 1 0
RX_DDC_FIFO_CONFIG0
R/W-52h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1431. Register 48 Field Descriptions
Bit Field Type Reset Description
7-0
RX_DDC_FIFO_C
ONFIG0
R/W 52h
RX DDC FIFO Configuration0. Value dependent on
decimation factor. Optimal value automatically determined if
System Configuration Macros are used.