Texas Instruments AFE79 Series - 2.12.65 Register 31 Eh (offset = 31 Eh) [reset = 0 h]; 2.12.66 Register 31 Fh (offset = 31 Fh) [reset = 0 h]; 2.12.67 Register 320 h (offset = 320 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.12.65 Register 31Eh (offset = 31Eh) [reset = 0h]
Figure 2-1268. Register 31Eh
7 6 5 4 3 2 1 0
TX_DUC_DAC_DITHER_CONFI
G2
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1280. Register 31E Field Descriptions
Bit Field Type Reset Description
1-0
TX_DUC_DAC_DI
THER_CONFIG2
R/W 0h
DAC data dither bandwidth control
0: regular
1: twice the regular bandwidth
2.12.66 Register 31Fh (offset = 31Fh) [reset = 0h]
Figure 2-1269. Register 31Fh
7 6 5 4 3 2 1 0
TX_DUC_DAC_DITHER_CONFIG4 TX_DUC_DAC_DITHER_CONFI
G3
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1281. Register 31F Field Descriptions
Bit Field Type Reset Description
4-2
TX_DUC_DAC_DI
THER_CONFIG4
R/W 0h
Fine amplitude scale control for DAC data dither.
0: 1 (default);
1: scaling of 3/4 (approx. -2.5 dB)
2: scaling of 5/4 (approx. +1.9 dB)
1-0
TX_DUC_DAC_DI
THER_CONFIG3
R/W 0h
Coase amplitude scale control for DAC data dither, in 6 dB
steps
0: -6 dBFS
1: -12 dBFS
2: -18 dBFS
3: -24 dBFS
2.12.67 Register 320h (offset = 320h) [reset = 0h]
Figure 2-1270. Register 320h
7 6 5 4 3 2 1 0
TX_DUC_DAC_DITHER_FCW0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1282. Register 320 Field Descriptions
Bit Field Type Reset Description
3-0
TX_DUC_DAC_DI
THER_FCW0
R/W 0h
Frequency shift control for the DAC data dither signal. Valid
range of values 0 to 8.
Value of k: frequency shift of k*Fdac/16